The present invention relates to a semiconductor memory device and, more particularly, to a dynamic memory device with a large capacity.
Semiconductor devices are known in which a unit memory device is comprised of a single transistor e.g. a MOS transistor, and a capacitive memory element interconnected to each other. Such known memory devices are of the type in which a semiconductor capacitive element is formed adjacent a signal MOS transistor and the writing and reading operations to and from the capacitive element are performed by controlling the gate voltage of the MOS transistor. However, in such type memory devices, the occupied area of the unit memory device on the semiconductor substrate is large. This prevents high density integration of the memory device. Another known memory device is of the type in which a capacitor electrode is formed on a part of the surface of a semiconductor substrate through an SiO.sub.2 layer. The surface of the semiconductor substrate facing the capacitor electrode, and the SiO.sub.2 layer are combined to form a semiconductive capacitive element, and the channel region of a MOS transistor (the semiconductor region between the source and drain of an ordinary MOS transistor) adjacent the capacitive element is directly coupled with the semiconductor substrate surface facing the capcitor electrode. A memory device of this kind is treated in the paper entitled "SURFACE CHARGE RAM SYSTEM" by W. E. Engeler, J. J. Tiemann and R. D. Baertsch, on pages 18 to 19 of DIGEST OF TECHNICAL PAPERS by 1972 IEEE International Solid-State Circuits Conference.
For memory arrays assembled in matrix fashion from a number of those memory elements, a high rate of reading and writing operation cycles is necessary. To this end, the occupied region of the individual memory element and the parasitic capacitance associated with an address selection line as well must be minimized. It was confirmed that, to satisfy those requirements, the address selection line must be connected with the gate electrode of the MOS transistor, over the storage electrode or the capacitor electrode.
Accordingly, an object of the present invention is to provide a semiconductor memory device in which the connection position of the gate electrode of a MOS transistor to an external conductor is so selected as to minimize the occupied region of a unit memory cell.
The present invention may be briefly summarized as involving a semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a memory element including a first insulating layer formed on a part of the surface of the substrate of the first conductivity type, a first electrode formed on the insulating layer and a surface region which serves as an electrode on the substrate facing the first electrode; a semiconductor region of a second conductivity type formed in the substrate spaced from the surface region of the substrate and connected to a first external conductor; a second insulating layer over the surface of the substrate between the semiconductor region of the second conductivity and the surface region of the substrate; a third insulating layer provided on the first electrode; a second electrode including first and second portions being continuous to each other, the first portion being disposed on the second insulating layer and the second portion on the third insulating layer; and an electrode contacting the second portion of the second electrode over the surface region and connected to a second external conductor.
Other features and objects of the present invention will be apparent from the following description taken in connection with the accompanying drawings, in which: